Intel : STA Engineer(1 No)
• Strong hands-on experience with industry standard STA tools such as Primetime and Tempus
• Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation
• Industry standard Synthesis and Place and Route Flows
• Key Timing aspects including cross talk, POCV, AOCV, OCV, MMMC and other timing-checks applied for deep-submicron designs, margins and constraints
• Good knowledge of digital circuit design and physical design methodologies such Place and Route, IR/EM Power Analysis, Clock Tree Synthesis
• Familiarity with ECO techniques and implementation
• Working experience in flow and infrastructure development for timing closure of block and chip-level
• Familiarity with circuit modeling, including SPICE models and worst-case corner selection
• Experience with large design STA and serdes/high-speed interfaces
• Good understanding of DFT flow