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Intel : STA Engineer(1 No)

Date:  27-Jun-2022
Location:  California
State:  San
Country:  US
Company:  LTTS

•    Strong hands-on experience with industry standard STA tools such as Primetime and Tempus
•    Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation
•    Industry standard Synthesis and Place and Route Flows
•    Key Timing aspects including cross talk, POCV, AOCV, OCV, MMMC and other timing-checks applied for deep-submicron designs, margins and constraints
•    Good knowledge of digital circuit design and physical design methodologies such Place and Route, IR/EM Power Analysis, Clock Tree Synthesis
•    Familiarity with ECO techniques and implementation
•    Working experience in flow and infrastructure development for timing closure of block and chip-level
•    Familiarity with circuit modeling, including SPICE models and worst-case corner selection
•    Experience with large design STA and serdes/high-speed interfaces
•    Good understanding of DFT flow