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Intel : Block PD PnR Engineer(3 Nos)

Date:  27-Jun-2022
Location:  California
State:  San
Country:  US
Company:  LTTS

•    Knowledgeable in Block Level / Partition level P&R implementation, including floor planning, clock & power distribution, timing closure, physical & electrical verification.
•    Strong knowledge of PD construction & analysis flows and methodology.
•    Shown ability to execute to stringent schedule & die size requirements.
•    be able to run through complete Physical design flow and handle complex design
•    Experience with advanced process technology nodes, more recent nodes
•    Extensive experience in developing and customizing high performance design flows using industry-standard EDA tools for logic and physical synthesis from Cadence, Synopsys, or a similar vendor.
•    Experience with driving EDA vendors to make tool improvements or new functions to meet advanced or unique design requirements.
•    Working knowledge of static timing analysis, high performance clock tree design flows, and PPA optimization methodologies is strongly preferred.
•    Excellent UNIX and scripting programming skills (Perl, Python, and/or TCL).