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Sr DFT Engineer / Lead DFT Engineers

Date:  18-Jul-2022
Location:  California
State:  Sant
Country:  US
Company:  LTTS

1.    Understanding EDT scan compression Methodology and very good hand on experience for on designs with compression.
2.    Very good understanding of hierarchical scan design, should have previous experience working on such designs
3.    Good understanding on any MBIST methodology,  knowledge on LV/Tessent Shell/Embedded -MBIST,  is a plus. 
4.    ATPG pattern generation and Simulation.
5.    MBIST pattern generation and simulation.
6.    Basic understanding of STA, for debugging SDF based simulations is a plus.
7.    Understanding of ATE test methodologies and performing diagnostic on ATE failures and silicon bring up on ATE
8.    ATPG DRC debug and coverage analysis