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RTL - Design Engineer / Lead

Date:  25-Jun-2022
Location:  California
State:  Fols
Country:  US
Company:  LTTS

Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
Evaluates new feature requests, Designs and develops IP features. Provides IP integration support to SoC customers and represents RTL team.
Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design.
You must be able to balance design trade-offs with modularity, scalability, global clocking/power-management and debug requirements, chassis compliance, power, area, and performance.
You will provide IP integration support to SOC customers and represent RTL and the IP team. You would be required to well versed in areas like Logic & coding quality metrics, power-aware designs (UPF), clock-crossing protocols and checks (CDC), emulation-friendly code (EFFM) and other Logic integration skills.
You would also be expected to have good scripting and automation skills to enhance productivity on the design execution.
* Experience with SRAM,DRAMs, Clk-power architectures, AON, Multi clock domains ets is a PLus.
* He should be able to Manage and Co-ordinate with the Off-shore team members.