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DV- Verification Lead

Date:  30-Jun-2022
Location:  California
State:  Milp
Country:  US
Company:  LTTS


JOB RESPONSIBILITIES
•    Develop test plans and test benches for module, subsystem and system level verification
•    Work closely with hardware, software and systems engineering teams to develop models and test cases, to debug failing tests, and to validate operation and performance in simulation and at the system level
•    Develop test bench components such as UVM agents and behavioral models for simulation and emulation platforms
•    Write in-depth test plans
•    Develop Directed and random test cases
•    Run and monitor test regressions
•    Measure and report coverage
•    Work with DSP and software designers on test environment and test vector generation
 
JOB REQUIREMENTS
•    Experience with UVM
•    Solid knowledge of System Verilog and C/C++
•    Experience with Assertion based Verification
•    Experience with using random stimulus in conjunction with functional coverage
•    Working knowledge of scripting languages such as Python
•    Excellent communication skills
 
REQUIRED SKILLS AND EXPERIENCE  
•    BSEE required / MSEE preferred
•    Minimum of 2 years of experience in SoC verification
 
PREFERRED 
•    UVM Verification Environment development experience for module or full system level
•    Strong Object Oriented Programming ability
•    Familiarity with ARM, MIPS, Risc-V, ARC or other processors
•    Familiar with AMBA Buses (APB/AHB/AXI)
•    Knowledge or experience with Ethernet packet processing
•    Experience with emulation platforms