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DFT Engineer

Date:  26-Jun-2022
Location:  California
State:  Sant
Country:  US
Company:  LTTS

•    Develop and support design for test (DFT) structures
•    Determine design for test approaches and develop DFT architecture
•    Design and verify DFT structures for memories (MBIST), digital and analog circuitry
•    Perform scan synthesis
•    Create, simulate and verify automatic generated test patterns (ATPG)
•    Create functional tests and corresponding test patterns
•    Knowledgeable regarding failure mechanisms in silicon production and creating test algorithms
•    Support silicon bring up of test patterns
•    Perform diagnosis of test patterns on silicon and optimize test time

Tools: (MUST – NO ALTERNATE OR DEVIATION FROM THE TOOL ACCEPTED)
•    Cadence Modus/Genus
•    Cadence Xcelium
Knowledge:
•    Scan DRC review/debug
•    Pattern generation (SA, TDF, Path delay etc.)
•    Coverage analysis
Silicon debug