DV lead Engineer

Date:  20 Apr 2024
Location:  Cedar Rapids
State:  IA
Country:  US
Company:  LTTS

Job Description & Skill Requirement:


 DV Lead  Engineers with GLS Experience: 
•    8+ years of Verification experience in SV/UVM based methodology..
•    Expertise in System Verilog and UVM based verification methodologies at SoC Level
•    Experience in OOP concepts, coverage based random verifications and Random Verifications

    *should have Experience in the GLS Based verifications and Validations. Should be well versed with GLS issues, Debugs and fixes.

•    Knowledge of industry standard Protocols like, AHB, APB, AMBA, AXI, I2C, UART, IO interconnect, memory controllers, CPU architecture is a plus
•    Needs to be a key team player, passionate, energetic, motivated, and self-driven



  • Any  Engineering Degree