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Digital Design Engineer

Date:  22-Nov-2022
Location:  California
State:  Sunn
Country:  US
Company:  LTTS

•3+ years of experience of in Digital System Design using HDL languages (Verilog, VHDL, SystemVerilog)
•Experience in the RTL coding 
•Experience in the Spyglass – Lint, CDC, DFT tools/flow
•Quick learner and easy to adopt the new environment and setup
•Added advantage if the TC have skill set of DC-Synthesis, SoC integration & PPA analysis
•Responsibilities are     
  •From the µArchitecture definition and develop the RTL
  •3rd Party IP integration and Lint, CDC, DFT clean up coordinating with External Vendor
  •Support to DV(Coverage, Bug Fix and analysis, PTPX) and PD cycle (SDC, UPF, Floorplan)
  •Power Measurement support – PPA analysis
  •Scripting to automate the RTL generation using FB internal tools