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DV- Sr Verification Engineers / Verification Lead

Date:  10-Aug-2022
Location:  California
State:  Fols
Country:  US
Company:  LTTS

•         The candidate will be part of silicon design team chartered with delivering IP and Subsystem designs to multiple server SOCs
•    10+  years experience
•    At least 5 years in UVM 
•    creating testbench from scratch by hand on at least one complex project.
•    Some C++ experience is desired
•    GPU experience not required but a plus
* Interact closely with the architecture and design teams, influencing product definition, implementation and validation. Create, define and develop system validation environment and test suites.- Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests. 
* The role requires the following attributes in the candidate:Hands-on verification experience and proficiency using SystemVerilog and UVM
* Proven track record in ASIC verification from environment development to tests developmentExperience in development and deployment of verification strategies and methodologies across teams and organizationsExperience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage. 
* He should be able to Manage and Co-ordinate with the Off-shore team members.