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Intel : Full Chip PD Engineer (1 No)

Date:  27-Jun-2022
Location:  California
State:  San
Country:  US
Company:  LTTS

•    Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
•    Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
•    Significant experience in developing and implementing Power-grid and Clock specifications
•    Deep Understanding of all aspects of Physical construction, Integration and Physical Verification
•    Deep knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes.
•    Power user of industry standard Physical Design & Synthesis tools
•    Shown understanding of scripting languages such as Perl/Tcl
•    Extensive knowledge of Extraction and STA methodology and tools